xmega + DMA (nelamurire)

[godFather89]

A mai folosit cineva controllerul DMA de pe xmega-uri. Vreau sa-l folosesc la proiectul din semnatura (xmega256A3 @ 32MHz + vs1053) pentru a mai elibera din sarcina procesorului si intampin niste probleme. Folosesc USARTE1 in master SPI mode pentru a transfera datele din memoria SRAM spre VS1053 fara interventia cpu-ului dar nu merge. Pare ca ar transfera datele, insa nici un rezultat (din pacate nu am osciloscop). Daca transfer datele traditional, merge cum trebuie.

 

playStart(&found);//DMACH is DMA.CH0DMA.CTRL |= DMA_ENABLE_bm;   DMACH.ADDRCTRL =   DMA_CH_SRCRELOAD_NONE_gc | DMA_CH_SRCDIR_INC_gc |   DMA_CH_DESTRELOAD_NONE_gc | DMA_CH_DESTDIR_FIXED_gc;      DMACH.TRIGSRC = DMA_CH_TRIGSRC_USARTE1_DRE_gc;DMACH.TRFCNT = 32; //32 byte block size   DMACH.DESTADDR0 = (((uint16_t)&USARTE1.DATA) >> 0) & 0xFF;DMACH.DESTADDR1 = (((uint16_t)&USARTE1.DATA) >> 8) & 0xFF;DMACH.DESTADDR2 = 0x00;   while (readNextData()) //load next sector{   count++;   //reload source address (buffer is 512 bytes)   DMACH.SRCADDR0 = (((uint16_t)playDataBuf) >> 0) & 0xFF;   DMACH.SRCADDR1 = (((uint16_t)playDataBuf) >> 8) & 0xFF;   DMACH.SRCADDR2 = 0x00; //internal SRAM                     for (uint8_t i=0; i<16; i++)   {      while ((PORTVS.IN & PIN_VS_DREQ_bm) == 0); //wait for vs1053            PORTVS.OUTCLR = PIN_VS_XDCS_bm;      DMACH.CTRLA = DMA_CH_ENABLE_bm | DMA_CH_SINGLE_bm | DMA_CH_BURSTLEN_1BYTE_gc;      //vsStream32Bytes(playDataBuf, i * 32); //traditional streaming works      uint8_t flags;      do      {         flags = (DMACH.CTRLB & (DMA_CH_ERRIF_bm | DMA_CH_TRNIF_bm));      } while (flags == 0);      PORTVS.OUTSET = PIN_VS_XDCS_bm;            DMACH.CTRLB |= ( flags );      if (flags & DMA_CH_ERRIF_bm) lcdPutStr_P(0, 4, PSTR("Error"));      if (flags & DMA_CH_TRNIF_bm) lcdPutStr_P(0, 5, PSTR("OK"));   }      }                        playStop(); 

[godFather89]

Am rezolvat. In caz ca mai intampina cineva problema asta: nu era la DMA, era de la XDCS. Pana la urma l-am lasat in permanenta activ (0 logic) si totul merge acum. Ciudat...