Indicatii referitoare la programarea FPGA.(FSM)

[Vizitator csimuleac]

Salutare, mi-am achizitionar recent un FPGA Spartan 3E-1600 de la Digilent si momentan nu am reusit sa comunic deloc cu ea. Lucrez in Xilinx ISE 11 in verilog si momentan am gasit un cod pe internet pentru un FSM dar nu stiu cu ce se manaca si ce ar trebui sa faca(nu prea le am cu HDL-urile).M-am oprit la el deoarece mi-a mers perfect pana la generarea fisierului .bit, am mai cautat programe dar aveam tot felul de warninguri sau errori. As dori daca stie cineva sa se uita peste cod si sa-mi spuna ce face sau ce ar trebuii sa faca, eu vreau sa-l descarc pe placa si sa comunic cu ea, pentru asta imi trebuie fisierul de constrangeri (UCF).

 

Acesta este codul FSM-ului.

 

module FSM_Example (

// Inputs:

Clock, // Master clock

Reset, // Master reset (active high)

A,

B,

C,

// Outputs:

D,

E,

F

);

 

// Port mode declarations:

// Inputs:

input Clock;

input Reset;

input A;

input B;

input C;

 

// Outputs:

output D;

output E;

output F;

// Registered identifiers:

// NOTE: Remove (or comment out) each line for which the 'assign' method is used

reg D;

reg E;

reg F;

// Functionality:

// Declare parameters to represent the state bit patterns

parameter s0 = 3'b000;

parameter s1 = 3'b001;

parameter s2 = 3'b010;

parameter s3 = 3'b011;

parameter s4 = 3'b100;

 

// Declare outputs of each circuit block

reg [2] State, NextState;

 

 

// State register

always @ (posedge Clock or posedge Reset)

if (Reset)

r$State <= p$s0;

else

State <= NextState;

 

// Output decoder

always @ (State) begin

D <= (State == s1 || State == s4);

E <= (State == s2);

F <= (State == s3);

end

 

// Next state decoder

always @ (State or A or B or C)

case (State)

s0: NextState <= (A) ? s4 : s1;

s1: NextState <= s2;

s2: NextState <= s3;

s3: if (cool.gif

NextState <= © ? s4 : s0;

else

NextState <= s3;

s4: NextState <= s0;

default: NextState <= s0;

endcase

endmodule

 

 

Iar aici este codul pentru modulul de test.

 

 

module FSM_Example_TESTBENCH;

// Input stimulus:

reg Clock;

reg Reset;

reg A;

reg B;

reg C;

// Output connections:

wire D;

wire E;

wire F;

// Set the maximum number of characters in the statename string

parameter MaxChars = 4;

// Create the "StateName" identifier (must declare the total

// number of bits... eight bits per character)

reg [8*MaxChars-1 : 0] StateName;

//Instantiate the DUT (device under test):

FSM_Example DUT (

// Inputs:

.Clock ( Clock ),

.Reset ( Reset ),

.A ( A ),

.B ( B ),

.C ( C ),

 

// Outputs:

.D ( D ),

.E ( E ),

.F ( F )

);

// Specify input stimulus:

initial begin

// Initial values for input stimulus:

Clock = 0;

Reset = 1;

A = 1'b0;

B = 1'b0;

C = 1'b0;

// Take out of reset

#10 Reset = 0;

// Wait until state s3, wait another

// period, then assert C

wait (DUT.State==DUT.s3) #10 C = 1;

// Deassert C

#10 C = 0;

// Assert B, then deassert

#10 B = 1;

#10 B = 0;

// Assert C

#10 C = 1;

// Wait until state s3, wait another

// period, then assert B

wait (DUT.State==DUT.s3) #10 B = 1;

// Wait until state s0 then stop

wait (DUT.State==DUT.s0) #10 $finish;

end

// Template for master clock. Uncomment and modify signal name as needed.

// Remember to set the initial value of 'Clock' in the 'initial' block above.

always #5 Clock = ~Clock;

// Create human-readable labels for current state

always @ (DUT.State)

case (DUT.State)

3'b000: StateName = "S0";

3'b001: StateName = "S1";

3'b010: StateName = "S2";

3'b011: StateName = "S3";

3'b100: StateName = "S4";

default:StateName = "??";

endcase

endmodule

 

am atasat ambele fisiere daca sunt doritori sa le incerce sa-mi lase un mesaj. Va multumesc