Help cu watchdog timer?????

[Mar]

As vrea sa introduc in programul meu o secventa cu watchdog timer, va rog sa ma ajutati si pe mine cu mai multe detalii. Din cite stiu eu trebuie sa:setez PSAsetez prescalerul(PSA si prescalerul din registrul OPTION_REG)Mai trebuie ceva?Multumesc

[Cristiano]

In afara de ce ai mentionat deja, trebuie sa mai dai cate un CLRWDT din cand in cand (si anume la intervale care sunt mai scurte decat perioada minima a ceasului de garda, care e de aproximativ 10 .. 20ms - vezi foaia de catalog, inmultita cu valoarea aleasa pentru postscaler).

[Mar]

Daca poti sa fi mai explicit te rog ca nu stiu nimic de ceasul de garda si postscaler Multumesc

[Mar]

Adica daca setez prescalerul la 0,5 sec., trebuie sa dau clrwdt inainte de 0,5 sec.?

[Cristiano]

Daca poti sa fi mai explicit te rog ca nu stiu nimic de ceasul de garda si postscaler

Multumesc

 

Pai de ce nu stii nimic, e explicat in foaia de catalog. In momentul in care pui o intrebare, ar trebui sa fi citit deja ce scrie acolo.

 

An 8-bit counter is available as a prescaler for the

Timer0 module, or as a postscaler for the Watchdog

Timer. A prescaler assignment for the Timer0 module

means that there is no postscaler for the Watchdog

Timer, and vice-versa.

The PSA and PS2:PS0 bits (OPTION<3:0>) determine

the prescaler assignment and prescale ratio.

The watchdog timer is a free running on-chip RC oscillator

which does not require any external components.

This RC oscillator is separate from the RC oscillator of

the CLKIN pin. That means that the WDT will run, even

if the clock on the OSC1 and OSC2 pins of the device

has been stopped, for example, by execution of a

SLEEP instruction. During normal operation, a WDT

time out generates a device RESET. If the device is in

SLEEP mode, a WDT time out causes the device to

wake-up and continue with normal operation. The WDT

can be permanently disabled by programming the configuration

bit WDTE as clear (Section 14.1).

14.7.1 WDT PERIOD

The WDT has a nominal time out period of 18 ms (with

no prescaler). The time out periods vary with temperature,

VDD and process variations from part to part (see

DC Specifications, Table 17-7). If longer time out periods

are desired, a postscaler with a division ratio of up

to 1:128 can be assigned to the WDT under software

control by writing to the OPTION register. Thus, time

out periods up to 2.3 seconds can be realized.

The CLRWDT and SLEEP instructions clear the WDT

and the postscaler, if assigned to the WDT, and prevent

it from timing out and generating a device RESET.

The TO bit in the STATUS register will be cleared upon

a Watchdog Timer time out.

14.7.2 WDT PROGRAMMING

CONSIDERATIONS

It should also be taken in account that under worst case

conditions (VDD = Min., Temperature = Max., max.

WDT postscaler) it may take several seconds before a

WDT time out occurs.

 

Trebuie sa rulezi periodic CLRWDT, inainte ca perioada de time-out sa expire (in caz ca doresti resetare la latch-up / erori in program), ori il poti lasa intentionat sa expire (mod low-power). Ceasul de garda e pus pentru siguranta (in caz ca programul o ia razna ori cipul intra in latch-up, microcontroller-ul va fi resetat), ori pentru facilitarea unui consum redus (impreuna cu modul SLEEP - microcontroller-ul se va activa periodic pentru durate scurte, in restul timpului fiind in sleep).